This invention pertains to packages (e.g., chip carriers) that contain integrated circuits or other electronic circuits and, more particularly, to such a package wherein the electrical interconnections (e.g., pins or solder pads) are arranged in a virtual mirror cross over pattern. This invention also pertains to an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror cross over package are also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.
It is well known that the propagation delay between two points (i.e., the time it takes an electrical signal to travel between the two points) increases as the distance between the two points increases. Consequently, one factor that limits the speed of a bus in a computer or other information processing system is the distance between the various components that are coupled to the bus. More specifically, the bus master and slave devices that have the greatest physical separation on the bus is one factor that limits the maximum speed of the bus. Stated another way, for any given bus speed, the maximum physical separation between any bus master and slave device must be less than a predetermined distance, and that predetermined distance gets shorter and shorter as bus speed increases. While the spacing of bus components is not problematic at bus clock frequencies well below 100 MHZ, component spacing becomes critical at higher clock frequencies where it becomes imperative to keep component spacing to a minimum.
FIGS. 1 and 2 are plan views of prior art computer component interconnection systems wherein five interconnected xe2x80x9cnodesxe2x80x9d are illustrated. Referring to these figures, components 101, 102, 103 and 104 may be four processors and component 105 may be a memory/host bridge controller. These components are interconnected by bus 106 (FIG. 1) or bus 201 (FIG. 2). Components 101-104 typically extend several inches in the xe2x80x9czxe2x80x9d direction (out of the paper) and are separated by about two inches to accommodate large heat sinks. Consequently, the large separation of components in the xe2x80x9cxxe2x80x9d direction, which is required for the heat sinks, and the extension of the components in the xe2x80x9czxe2x80x9d direction results in a long xe2x80x9csignaling distancexe2x80x9d between components, which significantly limits the maximum speed of operation.
One technique for placing bus components close together is to use mirror image components placed on opposite sides of a thin substrate, such as a printed circuit board. Since mirror image components are only separated by the thickness of the substrate when interconnected in this manner, this technique brings the components very close together. The downside to the use of xe2x80x9ctrue mirror imagexe2x80x9d components is that they require the manufacturer to stock and test two separate part numbers; one for the standard component and another for its mirror image.
Accordingly, the invention described below allows multiple electronic components to be interconnected very close together, thereby reducing the propagation delay between components and permitting higher speed operation. This invention also permits identical components (for example, multiple CPU""s) in identical xe2x80x9cvirtual mirrorxe2x80x9d packages to be interconnected on opposite sides of a substrate, thereby eliminating the need for two separate xe2x80x9ctrue mirror imagexe2x80x9d packages. The invention described below also permits large heat sinks to be attached to the components for improved cooling. This invention also permits multiple bus systems, such a xe2x80x9cclusteredxe2x80x9d computer system, to be closely spaced together in an array for high speed operation not only on the individual system buses, but also on the inter-system bus.
Briefly, the invention is an information handling system including a substrate having first and second sides, wherein the first side of the substrate includes first and second system buses extending in a xe2x80x9cYxe2x80x9d direction, and an inter-system bus extending in an xe2x80x9cXxe2x80x9d direction substantially perpendicular to the xe2x80x9cYxe2x80x9d direction. A first chip carrier has a multiplicity of pairs of system connection points, wherein each pair of system connection points includes electrically interconnected first and second system connection points. The set of first system connection points is arranged in a first pattern adjacent a first edge of the first chip carrier, and the set of second system connection points is arranged in a second pattern adjacent a second edge of the first chip carrier, such that the second pattern is the virtual mirror of the first pattern. The set of first system connection points is coupled to the first system bus. The first chip carrier also has a multiplicity of pairs of inter-system connection points, wherein each pair of inter-system connection points includes electrically interconnected first and second inter-system connection points. The set of first inter-system connection points is arranged in a third pattern adjacent a third edge of the first chip carrier, and the set of second inter-system connection points is arranged in a fourth pattern adjacent a fourth edge of the first chip carrier. The set of first inter-system connection points is coupled to the inter-system bus. A second chip carrier has a multiplicity of system connection points adjacent a first edge of the second chip carrier and is coupled to the second system bus. The second chip carrier has a multiplicity of inter-system connection points adjacent a second edge of the second chip carrier, which are coupled to the inter-system bus. A third chip carrier has a multiplicity of system connection points adjacent a first edge of the third chip carrier, which are coupled to the first system bus adjacent the first edge of the first chip carrier. A fourth chip carrier has a multiplicity of system connection points adjacent a first edge of the fourth chip carrier, which are coupled to the second system bus adjacent the first edge of the second chip carrier. The third chip carrier processes information on the first system bus, the fourth chip carrier processes information on the second system bus, and the first and second chip carriers communicate information between the first system bus and the second system bus.
In another embodiment, the invention is a virtual mirror cross over chip carrier that includes a first multiplicity of pairs of connection points, wherein each pair of connection points of the first multiplicity of connection point pairs includes electrically interconnected first and second connection points. The set of first connection points is arranged in a first pattern along a first edge of the chip carrier, and the set of second connection points is arranged in a second pattern along a second edge of the chip carrier, such that the second pattern is the virtual mirror of the first pattern. A second multiplicity of pairs of connection points is included, wherein each pair of connection points of the second multiplicity of connection point pairs includes electrically interconnected third and fourth connection points. The set of third connection points is arranged in a third pattern along a third edge of the chip carrier, and the set of fourth connection points is arranged in a fourth pattern along a second edge of the chip carrier.